Week 9

For this week, I have learned about the Clock Divider. The purpose of the clock divider is to make a delay. What make the clock divider so special is that, we can set how long we want to set the delay.

As the DE2 Board supply 50 Mhz of frequency for clock, it actually so fast. Our eyes cannot detect the changes that are done on the DE2 Board. so, we can make it slower by using the Clock divider. So, after making some research from the internet, I finally can come out with my own clock divider ( coding ). The figure below shows the coding for my clock divider. (1 second delay).

Basically, we just have to play with the period of the clock cycle. As the DE2 Board supply 50 Mhz frequency of clock, so that we can see that the clock cycle is about 20ns. This can be calculated by dividing 50 Mhz with one (1).

So, we can make a delay by create a new clock. The input for our clock is based on the clock supply from the DE2 Board. If we make a counter for 50 milion time, we can actually get the one second delay.

Week 8

For this week, I cannot continue my project because of I have many other work that need to do first.

Week 7

For this week, we (fourth year student) have to finish our proposal for our project to send to the coordinator. As for me, I have to state the objective of my project, the methods and approach that I taken to complete my project and the expected outcome from my project. So, the figure below show my proposal for my FYP. 

So, I hope that I can accomplish my project and will give some benefits to the users.

Week 6

For this week, I have continued my literature review from the internet. I find something that is interesting during my research that is to using the SDRAM from the DE2 Board. I think that the SDRAM will be useful for me to finish my project such that it can store and send the data through the DE2 Board.

The SDRAM Interface

The two SDRAM chips on the DE2-115 board each have a capacity of 512 Mbits (64 Mbytes). Each chip is organized as 8M x 16 bits x 4 banks. The signals needed to communicate with a chip are shown in Figure 2. All of the signals, except the clock, can be provided by the SDRAM Controller that can be generated by using the SOPC Builder. The clock signal is provided separately. It has to meet the clock-skew requirements as explained in section 7. Note that some signals are active low, which is denoted by the suffix N.

Other than that, the PIN at the DE2 Board also must be correctly assigned so that we can avoid DE2 Board from damage. You can download it here. This pin assignment we need to assign first before we can connect it to the DE2 Board. If we do not use all the pin, we still can make a save step that is by assign the unsigned pin as the tristate input.

Week 5

For this week, I have discussed some of the information that I need to know before I can continue my project. There is some step that I need to be done and that is the block diagram of my project. So, after making some revisions from the internet, I come out with my project flow chart.

My project is start from the program (Altera Quartus II ) in my computer. The program was in the Verilog HDL code. The code then will be transfer to the DE2 Board by using the USB Blaster. The DE2 Board then will receive the code and start functioning as the program told. Then some input will be set from the user to the DE2 Board ( actually the input is the time set for the alarm clock ). Then the DE2 board will transfer the data to the transmitter ( I still do not decide  which device I should use ). Then the transmitter will transmit the data to the receiver through the wireless connection. After the receiver receive the data, it will send the data to the earphone ( buzzer ). When the earphone receives the data, it will produce alarm sound according to the time set from the DE2 Board.