Week 4

For this week, I have learned a bit about the Verilog HDL language. This is important thing in my project because I will used verilog as the assembly language for the Altera QuartusII software to send the program to the DE2 Board.

The following is the code that I write to implement the 4-bit carry adder.

Verilog for Full_Adder

module Adder ( a, b, cin, Sum,Cout );

input a,b,cin;

output Sum,Cout;

assign Sum = (a^b^cin);

assign Cout = ( ( a & b ) | ( a & cin ) | ( b & cin ) );

endmodule

Verilog for 4-bit Full_Adder

module carryadder ( a, b, cin, Sum, Cout);

input[3:0] a, b;

input cin;

output[3:0] Sum;

output Cout;

wire c1, c2, c3;

Adder FA0 ( .cin(cin), .a(a[0]), .b(b[0]), .Sum(Sum[0]), .Cout(c1) );

Adder FA1 ( .cin(c1), .a(a[1]), .b(b[1]), .Sum(Sum[1]), .Cout(c2) );

Adder FA2 ( .cin(c2), .a(a[2]), .b(b[2]), .Sum(Sum[2]), .Cout(c3) );

Adder FA3 ( .cin(c3), .a(a[3]), .b(b[3]), .Sum(Sum[3]), .Cout(Cout) );

endmodule

 After that, I obtain the following 4-bit Carry Adder block diagram:

Figure 4.1: The Carry Adder block diagram.

After the stimulation, the following waveform is obtained:

Figure 4.1: The Carry Adder waveform.

The waveform obtained is correct if we compare it to the truth table.